28#define CURRENT_CLASS Teensy3x
35#define HAS_FLASH_READ 0
36#define HAS_HARDWARE_PWM 1
38#define HAS_INPUT_CAPTURE 0
40#define TIMER_INTR_NAME cmt_isr
48#define ISR(f) void f(void)
51#error IRremote requires at least 8 MHz on Teensy 3.x
63 SCB_AIRCR = 0x05FA0004;
69 uint8_t tmp __attribute__((unused)) = CMT_MSC;
73 void timerEnablePwm() {
74 CORE_PIN5_CONFIG = PORT_PCR_MUX(2) | PORT_PCR_DSE | PORT_PCR_SRE;
77 void timerDisablePwm() {
78 CORE_PIN5_CONFIG = PORT_PCR_MUX(1) | PORT_PCR_DSE | PORT_PCR_SRE;
81 void timerEnableIntr() {
82 NVIC_ENABLE_IRQ(IRQ_CMT);
85 void timerDisableIntr() {
86 NVIC_DISABLE_IRQ(IRQ_CMT);
89 static const uint32_t CMT_PPS_DIV = (F_BUS + 7999999U) / 8000000U;
92 SIM_SCGC4 |= SIM_SCGC4_CMT;
93 SIM_SOPT2 |= SIM_SOPT2_PTD7PAD;
95 CMT_PPS = CMT_PPS_DIV - 1U;
96 CMT_CGH1 = F_BUS / CMT_PPS_DIV / frequency * dutyCycle / 100U;
97 CMT_CGL1 = F_BUS / CMT_PPS_DIV / frequency * (100 - dutyCycle) / 100U;
106 void timerConfigNormal() {
107 SIM_SCGC4 |= SIM_SCGC4_CMT;
108 CMT_PPS = CMT_PPS_DIV - 1U;
114 CMT_CMD4 = (F_BUS / 160000U + CMT_PPS_DIV / 2U) / CMT_PPS_DIV - 31U;
int8_t dutycycle_t
Type for duty cycle in percent.
uint32_t frequency_t
Type for modulation frequency in Hz.
This class serves as an HAL (Hardware Abstraction Layer).